Intel’s “Father Of All” Xe HP MCM GPU Pictured With An Absolutely Massive 3696mm² Package

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We finally have our first glimpse of the absolutely mammoth MCM-based Xe HP GPU that Intel is building in its labs. The package and a deliberately down-rezzed image of the testing lab were tweeted a while ago by Intel’s Chief Architect Raja Koduri along with the enigmatic Jim Keller. The term “baap of all” is one we have seen (and heard) before from Raja so it allowed us to quickly connect the dots. The father of all GPUs just got its first picture taken and it’s an absolute beast.

Intel Xe HP ‘father of all’ MCM GPU can easily hit 2000mm² in total die size and features 16-bit float

Back in December 2019 (which seems almost a lifetime away), Raja Koduri sent out the following tweet with his team in Bangalore “crossing a significant milestone” in designing what is easily one of the largest silicons in the world. The key takeaway here, however, was that this is the Intel Xe HP GPU as Raja clearly states in his tweet. He christened this GPU, “the baap of all”, which is Hindi/Urdu for “father of all”.

Fast forward a few months, and he recently tweeted the following deck, complete with a picture of the package and the legendary Jim Keller. The picture of Raja in the image has been tastefully derezzed to make it impossible for any sleuthing and the picture of Jim Keller has a shallow depth of focus for the same reason, but the picture of the actual GPU package is crystal clear. Interestingly, the package features an LGA design. This might just be for testing purposes or could be the actual delivery format for enterprise uses. X (Chi) is the next letter after Phi after all – if you know what I mean. Raja also confirmed the support of 16-bit float with this tweet for the Intel Xe HP GPU – which is pretty essential for AI and deep learning applications.

I absolutely love the fact that the camera is stationed almost perfectly centered and a convenient scale reference is given as well. It’s almost as if Raja *wants* us sleuths to figure things out. Well, firing up our trusty pixel counting algos, and using the conservative estimate for an AA battery (49.2mm in length), we arrived at the following estimations (customary warning: small deviations in perspective and skewness can result in large deviations in the final numbers, the numbers given here are just for early reference purposes):

The shaded area under the heat spreader is roughly 2373mm² large.

The entire chip measured a resounding 3696mm² in our calculation. It is roughly 1 double AA cell in length and roughly 53.6% larger than a double AA cell in width. This results in an estimation of 48.9mm by 75.6mm for the height and width respectively. We also calculated the usable area under the heat spreader, which came out to roughly 2373mm². Assuming Intel isn’t going for too tight a fit, you are easily looking at the actual silicon surface area hitting the 2000mm² mark! This is absolutely insane and will truly be the baap of all.

[Speculation] If we assume that Intel is utilizing close to the full heat spreader area of 2000mm² (and keep in mind they could easily be far under this limit right now), we can also arrive at a rough estimate of tiles. While it is unclear at this time how Intel Xe HP connects with Intel’s Ponte Vecchio GPU, if the two are connected and/or similar, then we are probably looking at either 4 tiles with 500mm² or 8 tiles with 250mm² to achieve the maximum surface area [/speculation]. Ponte Vecchio is slated to arrive in 2021 and will be built on the 7nm process.

What do you think of Intel’s ‘Father Of All’ Xe GPU?



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