# Adders

Adders

Most mathematical operations can be handled with addition. For example, subtraction can be performed by taking the two’s complement of a binary value, and then adding it to the binary value from which it was to be subtracted. Two numbers can be multiplied using multiple additions. Counting either up or down (incrementing or decrementing) can be performed with additions of 1 or -1.

Chapter 2 showed that binary addition is performed just like decimal addition, the only difference being that decimal has 10 numerals while binary has 2. When adding two digits in binary, a result greater than one generates an “overflow”, i.e., a one is added to the next position.
This produces a sum of 0 with a carry of 1 to the next position. A well-defined process such as this is easily realized with digital logic. Image below shows the block diagram of a system that takes two binary inputs, A and B, and adds them together producing a bit for the sum and a bit indicating whether or not a carry occurred. This well known circuit is commonly referred to as a half-adder. With two inputs, there are four possible patterns of ones and zeros. A truth table can be derived from the image above from which the Boolean expressions can be developed to realize this system. The simplicity of a two-input truth table makes the use of a Karnaugh map unnecessary. Examining the Sum column shows that we should have an output of one when A=0 and B=1 and when A=1 and B=0.
This gives us the following SOP expression: Note that the output Sum is also equivalent to the 2-input XOR gate. For Carryout, the output equals 1 only when both A and B are equal to one. This matches the operation of the AND gate. Image below presents the logic circuit for half-adders The half-adder works fine if we’re trying to add two bits together, a situation that typically occurs only in the rightmost column of a multibit addition. The remaining columns have the potential of adding a third bit, the carry from a previous column. For example, assume we want to add two four bit numbers, A = 01102 and B = 10112. The addition would go something like that shown to the left.
Adding the least significant bits of a multi-bit value uses the halfadder described above. Each input to the half-adder takes one of the least significant bits from each number. The outputs are the least significant digit of the sum and a possible carry to the next column.
What is needed for the remaining columns is an adder similar to the Half-adder that can add two bits along with a carry from the previous column to produce a Sum and the Carryout to the next column.
Image below represents this operation where An is the bit in the nth position of A, Bn is the bit in the nth position of B, and Sn is the bit in the nth position in the resulting sum, S.
Notice that a Carryout from the addition of a pair of bits goes into the carry input of the adder for the next bit. We will call the input Carryin. This implies that we need to create a circuit that can add three bits, An, Bn, and Carryin from the n-1 position. This adder has two outputs, the sum and the Carryout to the n+1 position. The resulting circuit is called a full adder. A block diagram of the full adder is shown in image below  With three inputs there are 23 = 8 possible patterns of ones and zeros that could be input to our full adder. Table 8-1 lists these combinations along with the results of their addition which range from 0 to 310. The two-digit binary result in the last column of this table can be broken into its components, the sum and a carry to the next bit position. This gives us two truth tables, one for the Sum and one for the Carryout.
Sum and Carryout Truth Tables for a Full Adder With three inputs, a Karnaugh map can be use to create the logic expressions. One Karnaugh map will be needed for each output of the circuit. Image below presents the Karnaugh maps for the Sum and the Carryout outputs of our full adder where Cin represents the Carryin input. The Carryout Karnaugh map has three rectangles, each containing two cells and all three overlapping on the cell defined by A=1, B=1, and Cin=1. The Karnaugh map for the Sum is less promising. In fact, there is no way to make a more complex 3-input Karnaugh map than the one that exists for the Sum output of the full adder.
The addition or removal of a ‘1’ in any cell of the map will result in a simpler expression. The four single-cell rectangles result in the four products of the SOP expression for the Sum output shown following the Carryout expression.  Image below presents the circuit for the full adder: Now we have the building blocks to create an adder of any size. For example, a 16-bit adder is made by using a half adder for the least significant bit followed by fifteen full adders daisy-chained through their carries for the remaining fifteen bits.
This method of creating adders has a slight drawback, however. Just as with the addition of binary numbers on paper, the sum of the higherorder bits cannot be determined until the carry from the lower-order bits has been calculated and propagated through the higher stages.
Modern adders use additional logic to predict whether the higher-order bits should expect a carry or not well before the sum of the lower-order bits is calculated. These adders are called carry look ahead adders.

## NOT Gate

This logic gate, sometimes referred to as an inverter, is the only one in that has a …