Memory-Processor Interfacing

Memory-Processor Interfacing

The previous topic presented the input and output lines for a memory device. These lines are shared across all of the devices that communicate with the processor. If you look at the electrical traces across the surface of a motherboard, you should see collections of traces running together in parallel from the processor to then from one memory device to the next.

These groups of wires are referred to as the bus, which is an extension of the internal structure of the processor. This section discusses how the memory devices share the bus.

Buses

In order to communicate with memory, a processor needs three types of connections: data, address, and control. The data lines are the electrical connections used to send data to or receive data from memory. There is an individual connection or wire for each bit of data.

For example, if the memory of a particular system has 8 latches per memory location, i.e., 8 columns in the memory array, then it can store 8-bit data and has 8 individual wires with which to transfer data.

The address lines are controlled by the processor and are used to specify which memory location the processor wishes to communicate with. The address is an unsigned binary integer that identifies a unique location where data elements are to be stored or retrieved. Since this unique location could be in any one of the memory devices, the address lines are also used to specify which memory device is enabled.

The control lines consist of the signals that manage the transfer of data. At a minimum, they specify the timing and direction of the data transfer. The processor also controls this group of lines. Image below presents the simplest connection of a single memory device to a processor with n data lines and m address lines.

Unfortunately, the configuration of image below only works with systems that have a single memory device. This is not very common. For example, a processor may interface with a BIOS stored in a nonvolatile memory while its programs and data are stored in the volatile memory of a RAM stick.

In addition, it may use the bus to communicate with devices such as the hard drive or video card. All of these devices share the data, address, and control lines of the bus. (BIOS stand for Basic Input/Output System and it is the low-level code used to start the processor when it is first powered up.)

A method had to be developed to allow a processor to communicate to multiple memory devices across the same set of wires. If this wasn’t done, the processor would need a separate set of data, address, and control lines for each device placing an enormous burden on circuit board designers for routing wires.

By using a bus, the processor can communicate with exactly one device at a time even though it is physically connected to many devices. If only one device on the bus is enabled at a time, the processor can perform a successful data transfer. If two devices tried to drive the data lines simultaneously, the result would be lost data in a condition called bus contention.

Image below presents a situation where data is being read from memory device 1 while memory device 2 remains “disconnected” from the bus. Disconnected is in quotes because the physical connection is still present; it just doesn’t have an electrical connection across which data can pass.

Notice that image below shows that the only lines disconnected from the bus are the data lines. This is because bus contention only occurs when multiple devices are trying to output to the same lines at the same time. Since only the microprocessor outputs to the address and control lines, they can remain connected.

In order for this scheme to work, an additional control signal must be sent to each of the memory devices telling them when to be connected to the bus and when to be disconnected. This control signal is called a chip select.

A chip select is an active low signal connected to the enable input of the memory device. If the chip select is high, the memory device remains idle and its data lines are disconnected from the bus. When the processor wants to communicate with the memory device, it pulls that device’s chip select low thereby enabling it and connecting it to the bus.

Each memory device has its own chip select, and at no time do two chip selects go low at the same time. For example, table below shows the only possible values of the chip selects for a system with four memory devices.

The disconnection of the data lines is performed using tristate outputs for the data lines of the memory chips. A tristate output is digital output with a third state added to it. This output can be a logic 1, a logic 0, or a third state that acts as a high impedance or open circuit. It is like someone opened a switch and nothing is connected.

This third state is controlled by the chip select. When the active low chip select equals 1, data lines are set to high impedance, sometimes called the Z state. A chip select equal to 0 causes the data lines to be active and allow input or output.

In Figure 1, three different outputs are trying to drive the same wire. This results in bus contention, and the resulting data is unreadable. Figure 2 shows two of the outputs breaking their connection with the wire allowing the first output to have control of the line. This is the goal when multiple devices are driving a single line.

Figure 3 is the same as 2 except that the switches have been replaced with tristate outputs. With all but one of the outputs in a Z state, the top gate is free to drive the output without bus contention. The following sections describe how memory systems are designed using chip selects to take advantage of tristate outputs.

Memory Maps

Think of memory as several filing cabinets where each folder can contain a single piece of data. The size of the stored data, i.e., the number of bits that can be stored in a single memory location, is fixed and is equal to the number of columns in the memory array.

Each piece of data can be either code (part of a program) or data (variables or constants used in the program). Code and data are typically stored in the same memory, each piece of which is stored in a unique address or row of memory.

Some sections of memory are assigned to a predefined purpose which may place constraints on how they are arranged. For example, the BIOS from which the computer performs its initial startup sequence is located at a specific address range in non-volatile memory. Video memory may also be located at a specific address range.

System designers must have a method to describe the arrangement of memory in a system. Since multiple memory devices and different types of memory may be present in a single system, hardware designers need to be able to show what addresses correspond to which memory devices.

Software designers also need to have a way to show how the memory is being used. For example, which parts of memory will be used for the operating system, which parts will be used to store a program, or which parts will be used to store the data for a program.

System designers describe the use of memory with a memory map. A memory map represents a system’s memory with a long, vertical column. It is meant to model the memory array where the rows correspond to the memory locations. Within the full range of addresses are smaller partitions where the individual resources are present. Figure below presents two examples of memory maps.

The numbers along the left side of the memory map represent the addresses corresponding to each memory resource. The memory map should represent the full address range of the processor.

This full address range is referred to as the processor’s memory space, and its size is represented by the number of memory locations in the full range, i.e., 2m where m equals the number of address lines coming out of the processor. It is up to the designer whether the addresses go in ascending or descending order on the memory map.

As an example, let’s calculate the memory space of the processor represented by the memory map in Figure b above. The top address for this memory map is FFFFF16 = 1111 1111 1111 1111 11112. Since the processor accesses its highest address by setting all of its address lines to 1, we know that this particular processor has 20 address lines.

Therefore, its memory space is 220 = 1,048,57610 = 1 Meg. This means that all of the memory resources for this processor must be able to fit into 1 Meg without overlapping. In the next section, we will see how to compute the size of each partition of memory using the address lines.

For now, however, we can determine the size of a partition in memory by subtracting the low address from the high address, then adding one to account for the fact that the low address itself is a memory location. For example, the range of the BIOS in Figure a above starts at FF0016 = 65,28010 and goes up to FFFF16 = 65,53510. This means that the BIOS fits into 65,535 – 65,280 +1 = 256 memory locations.

It is vital to note that there is an exact method to selecting the upper and lower addresses for each of the ranges in the memory map. Take for example the memory range for Program A in Figure b above. The lower address is 2000016 while the upper address is 27FFF16. If we convert these addresses to binary, we should see a relationship.

2000016 = 0010 0000 0000 0000 00002
27FFF16 = 0010 0111 1111 1111 11112

It is not a coincidence that the upper five bits of these two addresses are identical while the remaining bits go from all zeros in the low address to all ones in the high address.

Converting the high and the low address of any one of the address ranges in Figure above should reveal the same characteristic. The next section shows how these most significant address bits are used to define which memory device is being selected.

Address Decoding

Address decoding is a method for using an address to enable a unique memory device while leaving all other devices idle. The method described here works for many more applications than memory though.

It is the same method that is used to identify which subnet a host computer is connected to based on its IP address. All address decoding schemes have one thing in common: the bits of the full address are divided into two groups, one group that is used to identify the memory device and one group that identifies the memory location within the selected memory device.

In order to determine how to divide the full address into these two groups of bits, we need to know how large the memory device is and how large the memory space is. Once we know the size of the memory device, then we know the number of bits that will be required from the full address to point to a memory location within the memory device.

Just as we calculated the size of the memory space of a processor, the size of the memory space of a device is calculated by raising 2 to a power equal to the number of address lines going to that device. For example, a memory device with 28 address lines going into it has 228 = 256 Meg locations. This means that 28 address bits from the full address must be used to identify a memory location within that device.

All of the remaining bits of the full address will be used to enable or disable the device. It is through these remaining address bits that we determine where the memory will be located within the memory map.

Table below presents a short list of memory sizes and the number of address lines required to access all of the locations within them. Remember that the memory size is simply equal to 2m where m is the number of address lines going into the device.

The division of the full address into two groups is done by dividing the full address into a group of most significant bits and least significant bits. The block diagram of an m-bit full address in Figure below shows how this is done. Each bit of the full address is represented with an where n is the bit position.

The bits used to enable the memory device are always the most significant bits while the bits used to access a memory location within the device are always the least significant bits.

Chip Select Hardware

What we need is a circuit that will enable a memory device whenever the full address is within the address range of the device and disable the memory device when the full address falls outside the address range of the device. This is where those most significant bits of the full address come into play.