Architecture/Functional block diagram of 8257 DMA controller

8257 DMA stands for 4-channel Direct Memory Access. It is specially designed by Intel for data transfer at the highest speed. Its initial function is to generate a peripheral request which allows the device to transfer the data directly to/from memory without any interference of the CPU.
With the use of a DMA controller, the device sends requests to the CPU to hold its data, sequential memory address and control bus, which helps the device to transfer data directly to/from the memory. The DMA data transfer is initiated only after receiving HLDA signal from the CPU.

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −
  • Primarily, when any device requires to send data between the device and the memory, the device need to send DMA request (DRQ) to DMA controller.
  • The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA signal.
  • Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the control over bus and acknowledges the HOLD request through HLDA signal.
  • when the CPU is in HOLD state with the HOLD request, the DMA controller has to control the operations over buses between the CPU, memory, and I/O devices.

Features of 8257

Here is a list of some of the prominent features of 8257 −
  • It has four channels which can be exhibited over four I/O devices.
  • Each channel has 16-bit address and 14-bit counter.
  • Data transfer of each channel can be taken up to 64kb.
  • Each channel can be programmed independently.
  • Each channel can perform certain specific actions i.e, read transfer, write transfer and verify transfer operations.
  • It produces MARK signal to the peripheral device that 128 bytes have been transferred.
  • It requires a single phase clock.
  • Its frequency ranges from 250Hz to 3MHz.
  • It performs operations in 2 modes, i.e., Master mode and Slave mode.

8257 Architecture

The following image shows the architecture of 8257 −
8257_architec

8257 Pin Description

The following image shows the pin diagram of a 8257 DMA controller −
8257_pin

DRQ0−DRQ3

As seen in the above diagram these are the four individual asynchronous channel DMA request inputs, which are used by the peripheral devices to obtain DMA services. When the rotating priority mode is selected, then DRQ0 will get the highest priority and DRQ3 will get the lowest priority among them.

DACKo − DACK3

These are the active-low and high (inactive)DMA acknowledge lines, which updates the peripheral requesting device service about the status of their request by the CPU. These lines can also act as strobe lines for the requesting devices.

Do − D7

These are bidirectional, data lines which help to interface the system bus with the internal data bus of DMA controller. In the Slave mode, command words are carried to 8257 and status words from 8257. In the master mode, the lines which are used to send higher byte of the generated address are sent to the latch. This address is further latched using ADSTB signal.

IOR

It is an active-low bidirectional tri-state input line, which helps to read the internal registers of 8257 by the CPU in the Slave mode. In the master mode, it also helps in reading the data from the peripheral devices during a memory write cycle.

IOW

It is an active low bi-direction tri-state line, which helps in loading the contents of the data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master mode, it is used to load the data to the peripheral devices during DMA memory read cycle.

CLK

It is a clock frequency signal which is required to perform internal operation of 8257.

RESET

This signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao – A3

These are the four least significant address lines. In the slave mode, they perform as an input, which selects one of the registers to be read or written. In the master mode, they are the outputs which contain four least significant memory address output lines produced by 8257.

CS

It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from 8257. In the master mode, it automatically disables the read/write operations to/from 8257.

A4 – A7

These are the higher nibble of the lower byte address generated by DMA in the master mode.

READY

It is an active-high asynchronous input signal, which helps DMA to make ready by inserting wait states.

HRQ

This signal helps to receive the hold request signal sent from the output device. In the slave mode, it is connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the CPU.

HLDA

It is the hold acknowledgement signal which indicates the DMA controller that the bus has been granted to the requesting peripheral by the CPU when it is set to 1.

MEMR

It is the low memory read signal, which is used to read the data from the addressed memory locations during DMA read cycles.

MEMW

It is the active-low three state signal which is used to write the data to the addressed memory location during DMA write operation.

ADST

This signal is used to convert the higher byte of the memory address generated by the DMA controller into the latches.

AEN

This signal is used to disable the address bus/data bus.

TC

It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral devices.

MARK

The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It indicates the current DMA cycle is the 128th cycle since the previous MARK output to the selected peripheral device.

Vcc

It is the power signal which is required for the operation of the circuit.
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