Architecture/Functional block diagram of 8087 Numeric Data Processor

8087 Architecture is divided into two groups, i.e., Control Unit (CU) and Numeric Extension Unit (NEU).
  • The control unit maintains the communication between the processor and the memory such as receiving and decoding instructions, reads and writes memory operands, maintains parallel queue, etc. All the coprocessor instructions are considered as ESC instructions, i.e., they start with ‘F’, the coprocessor only executes the ESC instructions while other instructions are handled by the microprocessor.
  • The numeric extension unit holds all the numeric processor instructions as the name suggests like arithmetic, logical, transcendental, and data transfer instructions. It consists of 8 register stack, which handles the operands for instructions and their results.
The architecture of 8087 coprocessor is as follows −
architecture_8087

8087 Pin Description

Let us first take a look at the pin diagram of 8087 −

The following list provides the Pin Description of 8087 −
pin_diagram
  • AD0– AD15− These are described as the time multiplexed address/data lines, which carry addresses at the time of the first clock cycle and data from the second clock cycle onwards.
  • A19/ S6– A16/S− These lines are the time multiplexed address/status lines. It functions same as the corresponding pins of 8086. TheS6, S4andS3are permanently high, while theS5is permanently low.
  • BHE¯/S7 − During the first clock cycle, the BHE¯/S7 is used to enable data on to the higher byte of the 8086 data bus and after that works as status lineS7.
  • QS1, QS0− These are considered as the queue status input signals which gives the status of instruction queue, their conditions as shown in the following table −
QS0 QS1 Status
0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent byte from the queue
  • INT − It is an interrupt signal, reaches to high when an unmasked exception has received during the execution.
  • BUSY − It is an output signal, when it is high it gives the indication as a busy state to the CPU.
  • READY − It is an input signal used to give instructions to the coprocessor in order to enquire about the readiness of the bus to receive data or not.
  • RESET − It is an input signal performs certain functions whenever required by the CPU. It is used to reject the internal activities of the coprocessor and prepare it for further execution whenever required by the CPU.
  • CLK − The CLK input provides the basic timings for the processor operation.
  • VCC − It is a power supply signal, which requires +5V supply for the operation of the circuit.
  • S0, S1, S2− These are considered as the status signals that gives the status of the operation that is used by the Bus Controller 8087 to produce memory and I/O control signals. These signals will be active during the fourth clock cycle.
S2 S1 S0 Queue Status
0 X X Unused
1 0 0 Unused
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
RQ/GT1& RQ/GT0− These are the Request/Grant signals used by the 8087 processors so that they can gain control of the bus from the host processor 8086/8088 for operand transfers.
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