The 8085 is an 8-bit general purpose microprocessor that can address 64K Byte of memory.
It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz.
The pins on the chip can be grouped into 6 groups:
Address Bus.
- Data Bus.
- Control and Status Signals.
- Power supply and frequency.
- Externally Initiated Signals.
- Serial I/O ports.
8086 Pin Diagram
Here is the pin diagram of 8086 microprocessor −
Let us now discuss the signals in detail −
Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal
Clock signal is provided through Pin-19. It gives timing to the processor to perform operations. It has different frequency for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15 carries higher order byte data. During the first clock cycle of operation, it carries 16-bit address and after that it carries 16-bit data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. While the first clock cycle is running, it carries 4-bit address and later it carries status signals.
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and helps in recognizing transfer of data using data bus D8-D15. during first clock cycle it becomes low and later it becomes active.
Read($\overline{RD}$)
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 32. The data that is transferred fromt he I/O devices is provided by an acknowledgement signal.. It is an active high signal. When it is high, it gives signals that the device is ready to transfer data. When it is low, it indicates that the device is not ready and should give a pause for some time.
RESET
It is available at pin 21 and is used to repeat the execution. Its present activity is immediately terminated by the processor. This signal will be active high for the first 4 clock cycles to RESET the microprocessor.
INTR
It is available at pin 18. It is considered as an interrupt request signal, which is sampled during the last clock cycle of each instruction in order to determine whether the processor is considering as an interrupt or not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is known as an edge triggered input, which specifies an interrupt request to the microprocessor.
$\overline{TEST}$
This signal is like wait state and is available at pin 23. When this signal is raised high, then the processor has to wait for IDLE state, otherwise the execution continues.
MN/$\overline{MX}$
It stands for Minimum/Maximum and is available at pin 33. It indicates as to which mode the processor has to operate.; when it is high, it works in the minimum mode and vice-a-versa( the process continues).
INTA
It is available at pin 24 which is provided by an interrupt acknowledgement signal . When the microprocessor receives this signal, it acknowledges the interrupt.
ALE
It stands for address enable latch which is available at pin 25. If any operation is performed by the processor everytime a positive pulse is produced. This signal indicates the availability of a valid address on the address/data lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The transreceiver is a device which is used to separate data from the address/data bus.
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides flow of data direction through the transreceiver. When it is high, data is transmitted out and vice-a-versa.
M/IO
This signal is used to differentiate between memory and I/O operations. When it is high, it indicates I/O operation and when it is low indicates the memory operation. It is available at pin 28.
WR
It stands for write signal and is available at pin 29. As the name indicates it is used to write the data into the memory or the output device based on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges the HOLD signal.
HOLD
This signal gives hints to the processor that external devices are requesting to access the address/data buses. It is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the status of instruction queue. Their conditions are shown in the following table −
QS0 | QS1 | Status |
---|---|---|
0 | 0 | No operation |
0 | 1 | First byte of opcode from the queue |
1 | 0 | Empty the queue |
1 | 1 | Subsequent byte from the queue |
S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus Controller 8288 to produce memory & I/O control signals. These are available at pin 26, 27, and 28. Following is the table showing their status −
S2 | S1 | S0 | Status |
---|---|---|---|
0 | 0 | 0 | Interrupt acknowledgement |
0 | 0 | 1 | I/O Read |
0 | 1 | 0 | I/O Write |
0 | 1 | 1 | Halt |
1 | 0 | 0 | Opcode fetch |
1 | 0 | 1 | Memory read |
1 | 1 | 0 | Memory write |
1 | 1 | 1 | Passive |
LOCK
Actually it is available at pin 29 where activation is done with the use of LOCK prefix on any instruction. When this signal is active, it raises alarm to the other processors not to ask the CPU to leave the system bus. It becomes active using the LOCK prefix on any instruction and is available at pin 29.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by other processors to send the request to the CPU to release the system bus. When the signal is received by CPU, it sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.