What is 8086 Interrupts and various types of Interrupts?

In certain situations when creating a program by the user we often find some sort of disturbances suddenly where the program stops abruptly. it might be due to some technical problems by hardware or software etc. This interrupt indicates immediate attention which alerts the microprocessor and instructs as to how to handle the interrupt. So, it is a method that creates a temporary halt at the time of program execution and allows peripheral devices to access the microprocessor. The microprocessor gives response to that interrupt with an ISR (Interrupt Service Routine) to handle the situation.
The following image shows the types of interrupts we have in a 8086 microprocessor −
interrupts

Hardware Interrupts

Hardware interrupt is probably caused by any one of peripheral device by sending a signal to the microprocessor with the help of a particular pin.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt which has lower priority. One more interrupt pin associated is INTA called interrupt acknowledge.

NMI

It is said to be a single non-maskable interrupt pin (NMI) which has higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt.
When this interrupt becomes activated, these actions could take place −
  • Completes the current instruction that is in progress.
  • Pushes the Flag register values on to the stack.
  • Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.
  • IP is loaded from the contents of the word location 00008H.
  • CS is loaded from the contents of the next word location 0000AH.
  • Interrupt flag and trap flag are reset to 0.

INTR

The INTR is a maskable interrupt because the microprocessor will get interrupted by using interrupt flag instruction where enabled instructions are ser properly. It should not be enabled using clear interrupt Flag instruction.
The INTR interrupt gets activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor function is to complete the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means that it gets the information from the external device from INTA to get ready and during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
  • Completes the current instruction first.
  • Activates INTA output and receives the interrupt type, say X.
  • Flag register value; CS value of the return address and IP value of the return address are pushed on to the stack.
  • IP value is loaded from the contents of word location X × 4
  • CS is loaded from the contents of the next word location.
  • Interrupt flag and trap flag is reset to 0

Software Interrupts

Some instructions are being included at the specified position into the program to create interrupts. In order to test the working of various interrupt handlers these interrupt instructions are used. It includes −

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
  • Flag register value is pushed on to the stack.
  • CS value of the return address and IP value of the return address are pushed on to the stack.
  • IP is loaded from the contents of the word location ‘type number’ × 4
  • CS is loaded from the contents of the next word location.
  • Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −
  • TYPE 0 interrupt represents division by zero situation.
  • TYPE 1 interrupt represents single-step execution during the debugging of a program.
  • TYPE 2 interrupt represents non-maskable NMI interrupt.
  • TYPE 3 interrupt represents break-point interrupt.
  • TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts from 32 to Type 255 are available for hardware and software interrupts.

INT 3-Break Point Interrupt Instruction

It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program in order to stop the normal ezecution of the program by interrupt when the processor reaches at that point. and follows the break-point procedure.
Its execution includes the following steps −
  • Flag register value is pushed on to the stack.
  • FS value of the return address and IP value of the return address are pushed on to the stack.
  • IP is loaded from the contents of the word location 3×4 = 0000CH
  • CS is loaded from the contents of the next word location.
  • Interrupt Flag and Trap Flag are reset to 0

INTO – Interrupt on overflow instruction

It is generally known as 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the name suggests it is a conditional interrupt instruction, i.e. checks the overflow condition of OF flag in the register and calls the interrupt handler when the overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number is 4. If the overflow flag is reset again, then the execution continues to the next instruction.
Its execution includes the following steps −
  • Flag register values are pushed on to the stack.
  • CS value of the return address and IP value of the return address are pushed on to the stack.
  • IP is loaded from the contents of word location 4×4 = 00010H
  • CS is loaded from the contents of the next word location.
  • Interrupt flag and Trap flag are reset to 0
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